Die Kerndaten des Cell-Chips sind da!
Sony, IBM und Toshiba haben das Geheimnis um den Cell-Chip gelüftet: Auf der International Solid State Circuits Conference (ISSCC) wurden die vollständigen Details zu dem vermeintlichen Prozessor-Wunder genannt, der auch in der PS3 seine Dienste verrichten wird. Der Prototyp ist gerade mal 221 Quadratmillimeter groß, wird mit 90 Nanometer-SOI-Technologie hergestellt und vereint 243 Millionen Transistoren. Nachfolgend findet ihr die weiteren technischen Daten, die wir im englischen Original belassen haben:
SUMMARY
- Cell is a breakthrough architectural design - featuring 8 Synergistic Processing Units (SPU) with Power-based core, with top clock speeds exceeding 4 GHz (as measured during initial laboratory testing).
- Cell is OS neutral - supporting multiple operating systems simultaneously
- Cell is a multicore chip comprising 8 SPUs and a 64-bit Power processor core capable of massive floating point processing
- Special circuit techniques, rules for modularity and reuse, customized clocking structures, and unique power and thermalmanagement concepts were applied to optimize the design
CELL is a Multi-Core Architecture
- Contains 8 SPUs each containing a 128 entry 128-bit register file and 256KB Local Store
- Contains 64-bit Power ArchitectureTM with VMX that is a dual thread SMT design-views system memory as a 10-way coherent threaded machine
- 2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
- 234 million transistors
- Prototype die size of 221mm2
- Fabricated with 90nanometer (nm) SOI process technology
- Cell is a modular architecture and floating point calculation capabilities can be adjusted by increasing or reducing the number of SPUs
CELL is a Broadband Architecture
- Compatible with 64b Power ArchitectureTM
- SPU is a RISC architecture with SIMD organization and Local Store
- 128+ concurrent transactions to memory per processor
- High speed internal element interconnect bus performing at 96B/cycle
CELL is a Real-Time Architecture
- Resource allocation (for Bandwidth Management)
- Locking caches (via Replacement Management Tables)
- Virtualization support with real time response characteristics across multiple operating systems running simultaneously
CELL is Security Enabled Architecture
- SPUs dynamically configurable as secure processors for flexible security programming
CELL is a Confluence of New Technologies
- Virtualization techniques to support conventional and real time applications
- Autonomic power management features
- Resource management for real time human interaction
- Smart memory flow controllers (DMA) to sustain bandwidth
SUMMARY
- Cell is a breakthrough architectural design - featuring 8 Synergistic Processing Units (SPU) with Power-based core, with top clock speeds exceeding 4 GHz (as measured during initial laboratory testing).
- Cell is OS neutral - supporting multiple operating systems simultaneously
- Cell is a multicore chip comprising 8 SPUs and a 64-bit Power processor core capable of massive floating point processing
- Special circuit techniques, rules for modularity and reuse, customized clocking structures, and unique power and thermalmanagement concepts were applied to optimize the design
CELL is a Multi-Core Architecture
- Contains 8 SPUs each containing a 128 entry 128-bit register file and 256KB Local Store
- Contains 64-bit Power ArchitectureTM with VMX that is a dual thread SMT design-views system memory as a 10-way coherent threaded machine
- 2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
- 234 million transistors
- Prototype die size of 221mm2
- Fabricated with 90nanometer (nm) SOI process technology
- Cell is a modular architecture and floating point calculation capabilities can be adjusted by increasing or reducing the number of SPUs
CELL is a Broadband Architecture
- Compatible with 64b Power ArchitectureTM
- SPU is a RISC architecture with SIMD organization and Local Store
- 128+ concurrent transactions to memory per processor
- High speed internal element interconnect bus performing at 96B/cycle
CELL is a Real-Time Architecture
- Resource allocation (for Bandwidth Management)
- Locking caches (via Replacement Management Tables)
- Virtualization support with real time response characteristics across multiple operating systems running simultaneously
CELL is Security Enabled Architecture
- SPUs dynamically configurable as secure processors for flexible security programming
CELL is a Confluence of New Technologies
- Virtualization techniques to support conventional and real time applications
- Autonomic power management features
- Resource management for real time human interaction
- Smart memory flow controllers (DMA) to sustain bandwidth
